The semiconductor industry has experienced technological advances that have permitted increases in density and/or complexity of semiconductor memory devices. Also, the technological advances have allowed decreases in power consumption and package sizes of various types of semiconductor memory devices. There is a continuing trend to employ and/or fabricate advanced semiconductor memory devices using techniques, materials, and devices that improve performance, reduce leakage current, and enhance overall scaling. Silicon-on-insulator (SOI) and bulk substrates are examples of materials that may be used to fabricate such semiconductor memory devices. Such semiconductor memory devices may include, for example, partially depleted (PD) devices, fully depleted (FD) devices, multiple gate devices (e.g., double, triple gate, or surrounding gate), and Fin-FET devices.
A semiconductor memory device may include a memory cell having a memory transistor with an electrically floating body region wherein electrical charge may be stored. When excess majority electrical charges carriers are stored in the electrically floating body region, the memory cell may store a logic high (e.g., binary “1” data state). When the electrical floating body region is depleted of majority electrical charge carriers, the memory cell may store a logic low (e.g., binary “0” data state). Also, a semiconductor memory device may be fabricated on silicon-on-insulator (SOI) substrates or bulk substrates (e.g., enabling body isolation). For example, a semiconductor memory device may be fabricated as a three-dimensional (3-D) device (e.g., a multiple gate device, a Fin-FET device, and a vertical pillar device).
In one conventional technique, the memory cell of the semiconductor memory device may be manufactured by an implantation process. During a conventional implantation process, defect structures may be produced in a silicon lattice of various regions of the memory cell of the semiconductor memory device. The defect structures formed during the implantation process may decrease retention time of majority charge carriers stored in the memory cell of the semiconductor memory device. Also, during a conventional implantation process, various regions of the memory cell may be doped with undesired doping concentrations. The undesired doping concentrations may thus produce undesired electrical properties for the memory cell of the semiconductor memory device. Further, the conventional implantation process may face lateral and vertical scaling challenges.
In view of the foregoing, it may be understood that there may be significant problems and shortcomings associated with conventional techniques for providing a semiconductor memory device.